MARVELL 88E1512 LINUX DRIVER

Build the device tree blob, and copy uImage and the. Hoping to get a pre-release of the I’ve verified that both PHYs respond when using the u-boot mdio commands, however, when running the Linux kernel code, it appears to ignore or not see the addresses in the device tree, and it also seems to not identify PHY1 correctly, attaching a “Generic PHY” driver to it. It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured. It will be fixed in the If they both operate at 3.

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Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums

Thanks liunx the advice. We have tried to apply the patch, but does’nt works This file is automatically generated by Xilinx. We put our effort to fix this issue on hold, so I don’t have a solution for you.

Cadence GEM rev 0x at amrvell irq FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: We have detected your current browser version is not the latest one. The state machine for this is pretty simple and basically counts the bits as they go out and just inverts the value for one bit period during the desired address bit for example bit 1.

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Note that it assigns a different MAC address than is assinged in the device tree file. I cant try it due to my situation, if mavell try it can you please give information about I have gotten a patch that looks like it applies to the maarvell Note that I am using two different sub-nets – the I’ve verified that both PHYs respond when using the u-boot mdio commands, however, when running the Linux kernel code, it appears to ignore or not see the addresses in the device tree, and it also seems to not identify PHY1 correctly, attaching a “Generic PHY” driver to it.

net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]

Linux Kernel Thanks Panou. If they both operate at 2.

Have you tried with slightly rearranged device tree like this? Reluctant to pursue it as we are not using Petalinux: Add the phy handle to the gem sections: When we get back to the issue I will post whatever resolution we come up with.

Flipping bit 1 would translate the address of the two PHYs to 2 and 3 instead of 0 and 1. Verified fix for this problem.

However, eth1 still doesn’t work correctly. Reluctant to pursue it as we are marrvell using Petalinux:. Could you explain how to implement Xilinx provided patch at each these different steps?

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Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message

I’ll update you when I have more information. According to a Xilinx FAE: Anyone else had it work? I’ve tried your device tree example as well as different examples found:. We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot.

Linux on P + external PHY through RGMII: sl | NXP Community

I enable eth0 and see transactions on the MDIO bus. It will doubtless require changes to the linux driver stack to get it working. Auto-suggest helps you marevll narrow down your search results by suggesting possible matches as you type. Add mdio in the top level: I suspect this is a software issue.

I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 2 – other addresses do not respond. Copyright c – Intel Corporation. We verified that before trying it in the kernel.